293 lines
4.2 KiB
ArmAsm
293 lines
4.2 KiB
ArmAsm
// +build amd64,!appengine,!gccgo
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// This is a translation of the gcc output of FloodyBerry's pure-C public
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// domain siphash implementation at https://github.com/floodyberry/siphash
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// This assembly code has been modified from the 64-bit output to the experiment 128-bit output.
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// SI = v0
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// AX = v1
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// CX = v2
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// DX = v3
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// func Hash128(k0, k1 uint64, b []byte) (r0 uint64, r1 uint64)
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TEXT ·Hash128(SB),4,$0-56
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MOVQ k0+0(FP),CX
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MOVQ $0x736F6D6570736575,R9
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MOVQ k1+8(FP),DI
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MOVQ $0x6C7967656E657261,BX
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MOVQ $0x646F72616E646F6D,AX
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MOVQ b_len+24(FP),DX
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XORQ $0xEE,AX
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MOVQ DX,R11
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MOVQ DX,R10
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XORQ CX,R9
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XORQ CX,BX
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MOVQ $0x7465646279746573,CX
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XORQ DI,AX
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XORQ DI,CX
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SHLQ $0x38,R11
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XORQ DI,DI
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MOVQ b_base+16(FP),SI
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ANDQ $0xFFFFFFFFFFFFFFF8,R10
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JE afterLoop
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XCHGQ AX,AX
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loopBody:
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MOVQ 0(SI)(DI*1),R8
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ADDQ AX,R9
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RORQ $0x33,AX
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XORQ R9,AX
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RORQ $0x20,R9
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ADDQ $0x8,DI
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XORQ R8,CX
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ADDQ CX,BX
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RORQ $0x30,CX
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XORQ BX,CX
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ADDQ AX,BX
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RORQ $0x2F,AX
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ADDQ CX,R9
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RORQ $0x2B,CX
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XORQ BX,AX
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XORQ R9,CX
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RORQ $0x20,BX
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ADDQ AX,R9
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ADDQ CX,BX
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RORQ $0x33,AX
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RORQ $0x30,CX
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XORQ R9,AX
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XORQ BX,CX
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RORQ $0x20,R9
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ADDQ AX,BX
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ADDQ CX,R9
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RORQ $0x2F,AX
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RORQ $0x2B,CX
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XORQ BX,AX
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RORQ $0x20,BX
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XORQ R9,CX
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XORQ R8,R9
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CMPQ R10,DI
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JA loopBody
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afterLoop:
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SUBQ R10,DX
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CMPQ DX,$0x7
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JA afterSwitch
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// no support for jump tables
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CMPQ DX,$0x7
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JE sw7
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CMPQ DX,$0x6
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JE sw6
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CMPQ DX,$0x5
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JE sw5
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CMPQ DX,$0x4
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JE sw4
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CMPQ DX,$0x3
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JE sw3
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CMPQ DX,$0x2
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JE sw2
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CMPQ DX,$0x1
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JE sw1
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JMP afterSwitch
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sw7: MOVBQZX 6(SI)(DI*1),DX
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SHLQ $0x30,DX
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ORQ DX,R11
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sw6: MOVBQZX 0x5(SI)(DI*1),DX
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SHLQ $0x28,DX
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ORQ DX,R11
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sw5: MOVBQZX 0x4(SI)(DI*1),DX
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SHLQ $0x20,DX
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ORQ DX,R11
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sw4: MOVBQZX 0x3(SI)(DI*1),DX
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SHLQ $0x18,DX
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ORQ DX,R11
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sw3: MOVBQZX 0x2(SI)(DI*1),DX
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SHLQ $0x10,DX
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ORQ DX,R11
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sw2: MOVBQZX 0x1(SI)(DI*1),DX
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SHLQ $0x8,DX
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ORQ DX,R11
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sw1: MOVBQZX 0(SI)(DI*1),DX
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ORQ DX,R11
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afterSwitch:
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LEAQ (AX)(R9*1),SI
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XORQ R11,CX
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RORQ $0x33,AX
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ADDQ CX,BX
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MOVQ CX,DX
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XORQ SI,AX
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RORQ $0x30,DX
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RORQ $0x20,SI
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LEAQ 0(BX)(AX*1),CX
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XORQ BX,DX
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RORQ $0x2F,AX
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ADDQ DX,SI
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RORQ $0x2B,DX
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XORQ CX,AX
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XORQ SI,DX
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RORQ $0x20,CX
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ADDQ AX,SI
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RORQ $0x33,AX
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ADDQ DX,CX
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XORQ SI,AX
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RORQ $0x30,DX
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RORQ $0x20,SI
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XORQ CX,DX
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ADDQ AX,CX
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RORQ $0x2F,AX
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ADDQ DX,SI
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XORQ CX,AX
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RORQ $0x2B,DX
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RORQ $0x20,CX
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XORQ SI,DX
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XORQ R11,SI
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XORB $0xEE,CL
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ADDQ AX,SI
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RORQ $0x33,AX
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ADDQ DX,CX
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RORQ $0x30,DX
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XORQ SI,AX
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XORQ CX,DX
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RORQ $0x20,SI
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ADDQ AX,CX
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ADDQ DX,SI
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RORQ $0x2F,AX
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RORQ $0x2B,DX
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XORQ CX,AX
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XORQ SI,DX
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RORQ $0x20,CX
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ADDQ AX,SI
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ADDQ DX,CX
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RORQ $0x33,AX
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RORQ $0x30,DX
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XORQ SI,AX
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RORQ $0x20,SI
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XORQ CX,DX
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ADDQ AX,CX
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RORQ $0x2F,AX
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ADDQ DX,SI
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RORQ $0x2B,DX
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XORQ CX,AX
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XORQ SI,DX
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RORQ $0x20,CX
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ADDQ AX,SI
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ADDQ DX,CX
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RORQ $0x33,AX
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RORQ $0x30,DX
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XORQ CX,DX
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XORQ SI,AX
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RORQ $0x20,SI
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ADDQ DX,SI
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ADDQ AX,CX
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RORQ $0x2F,AX
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XORQ CX,AX
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RORQ $0x2B,DX
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RORQ $0x20,CX
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XORQ SI,DX
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// gcc optimized the tail end of this function differently. However,
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// we need to preserve out registers to carry out the second stage of
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// the finalization. This is a duplicate of an earlier finalization
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// round.
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ADDQ AX,SI
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RORQ $0x33,AX
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ADDQ DX,CX
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RORQ $0x30,DX
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XORQ SI,AX
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XORQ CX,DX
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RORQ $0x20,SI
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ADDQ AX,CX
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ADDQ DX,SI
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RORQ $0x2F,AX
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RORQ $0x2B,DX
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XORQ CX,AX
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XORQ SI,DX
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RORQ $0x20,CX
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// Stuff the result into BX instead of AX as gcc had done
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MOVQ SI,BX
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XORQ AX,BX
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XORQ DX,BX
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XORQ CX,BX
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MOVQ BX,ret+40(FP)
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// Start the second finalization round
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XORB $0xDD,AL
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ADDQ AX,SI
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RORQ $0x33,AX
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ADDQ DX,CX
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RORQ $0x30,DX
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XORQ SI,AX
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XORQ CX,DX
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RORQ $0x20,SI
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ADDQ AX,CX
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ADDQ DX,SI
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RORQ $0x2F,AX
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RORQ $0x2B,DX
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XORQ CX,AX
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XORQ SI,DX
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RORQ $0x20,CX
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ADDQ AX,SI
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ADDQ DX,CX
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RORQ $0x33,AX
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RORQ $0x30,DX
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XORQ SI,AX
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RORQ $0x20,SI
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XORQ CX,DX
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ADDQ AX,CX
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RORQ $0x2F,AX
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ADDQ DX,SI
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RORQ $0x2B,DX
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XORQ CX,AX
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XORQ SI,DX
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RORQ $0x20,CX
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ADDQ AX,SI
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ADDQ DX,CX
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RORQ $0x33,AX
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RORQ $0x30,DX
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XORQ CX,DX
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XORQ SI,AX
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RORQ $0x20,SI
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ADDQ DX,SI
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ADDQ AX,CX
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RORQ $0x2F,AX
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XORQ CX,AX
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RORQ $0x2B,DX
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RORQ $0x20,CX
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XORQ SI,DX
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ADDQ AX,SI
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RORQ $0x33,AX
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ADDQ DX,CX
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RORQ $0x30,DX
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XORQ SI,AX
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XORQ CX,DX
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RORQ $0x20,SI
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ADDQ AX,CX
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ADDQ DX,SI
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RORQ $0x2F,AX
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RORQ $0x2B,DX
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XORQ CX,AX
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XORQ SI,DX
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RORQ $0x20,CX
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MOVQ SI,BX
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XORQ AX,BX
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XORQ DX,BX
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XORQ CX,BX
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MOVQ BX,ret1+48(FP)
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RET
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